- BTech/MTech in Electronics/Electrical Engineering
- Minimum 10 years of experience in CAD/ Tool Flow development
- A very good understanding of the Overall ASIC Design Flow
- Scripting in Perl and TCL experience is a MUST
- Must understand complete library design flow, Liberty Formats, Variation Formats, P&R/timing requirements of library, DFT/testing aspect of the design.
- Understanding of Timing Constraints
- Understanding of Common issues in 28nm and advanced nodes a plus.
Good to have:
- Experience characterization, circuit design & QA experience of Stdcells and Memory Design Kits is a plus.
- Ability to write verilog models and run verilog simulations for stdcells and memory
- Working experience with std cell and memory layout, familiarity with reviewing DRM, DRC/LVS results