Job: PHY RTL Principal ASIC Engineer

Title
PHY RTL Principal ASIC Engineer
Categories India
Salary No bar for Right Candidate
Location Bangalore
Job Information

Required Skills

  • Excellent background in the architecture and Micro-architecture of wireless baseband receivers.
  • Defined and implemented complete transceiver and the corresponding clocking, memory architecture, debug architecture for RF and Analog.
  • Implementation of filtering and decoding structures in RTL.
  • Performed tradeoff analysis on implementation options.
  • Good understanding of Digital Signal Processing and Communications theory.
  • Ability to analyze the impact of any architecture and propose options for implementation.
  • Experience with implementation of test structures for the Analog to Digital converters and interface to digital I/O.
  • Experience in design verification, validation of the design on FPGAs and post silicon validation.

Required Experience

  • E/M.Tech in Electronics Engineering.
  • 12-15 years of experience in digital PHY implementation.
  • Emphasis on signal processing / communications would be a plus.
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