In this challenging role, you will work on the following:
- Hands on with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, …)
- All aspects of Physical Design including Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
- Should be able to manage schedules, mentor the juniors and support cross-functional engineering effort to drive to signoff closure for tapeout
- Innovate on the flows to meet the QoR targets and ensure predictability
- Exposure to the latest design rules, processes and innovations need to close PPA on the advance nodes.
Desired Skills and Experience:
- Tech. / M. Tech. with 12-15 years of experience in Physical Design
- The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on SOC solutions technologies
- Should have handled Netlist to GDS II at Chip level for multiple tape outs
- Hands-on expertise with technology nodes like 28nm, 16nm and below
- Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with Encounter & Calibre
- Candidate should have exposure to chip power planning, bump and package planning
- Along with partitioning, candidate should have hands-on experience in Chip/block floor planning, placement optimizations, CTS and routing.
- Excellent understanding and hands on experience with physical verification (DRC/LVS/ERC/antenna) and other reliability checks(IR/EM/Xtalk)
- Hands-on experience in Full chip level signoff STA
- Being proficient in TCL, Perl scripting is a plus