In this challenging role, you will work on the following:
- Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, …)
- All aspects of Physical Design including Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
- Innovate on the flows to meet the QoR targets and ensure predictability
- Exposure to the latest design rules, processes and innovations need to close PPA on the advance nodes.
Desired Skills and Experience:
- Tech. / M. Tech. with 7-10 years of experience in Physical Design
- Should have handled Netlist to GDS II at Chip/block level for multiple tape outs
- Hands-on expertise with technology nodes like 28nm, 16nm and below
- Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with Encounter & Calibre
- Hands-on experience in Chip/block floorplanning, placement optimizations, CTS and routing
- Excellent understanding and hands on experience with physical verification (DRC/LVS/ERC/antenna) and other reliability checks(IR/EM/Xtalk)
- Hands-on experience in block/top level signoff STA
- Exposure in physical implementation of timing/functional ECO’s
- Being proficient in TCL, Perl scripting is a plus