Job: STA/Synthesis Implementation ASIC Principal/Sr. Principal Engineer

STA/Synthesis Implementation ASIC Principal/Sr. Principal Engineer
Categories India
Salary No bar for Right Candidate
Location Bangalore
Job Information

Required Skills:

  • Background in the synthesis and timing closure of large digital designs with multiple clock domains.
  • Development in timing constraints for multiple clock domain and derived clocks.
  • Implementation and synthesis of digital designs for low power implementation.
  • Scan insertion and Memory Bist insertion experience.
  • Low power design techniques a plus.
  • Working with place and route team on translation of the constraints and timing closure activities.
  • Working on generating timing and functional ECOs for timing signoff.
  • Experience with LEC (functional equivalence signoff).
  • Static timing closure experience for tapeout signoff.


Required Experience:

  • BE/M.Tech in Electronics Engineering.
  • 12-15 years of experience in digital implementation for sub-micron processes.
  • Expertise in digital circuit design would be a plus.
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